As part of our on-site training series, we offer "IC Design Show Stoppers." This is a one-day training course that teaches your design team how to eliminate the biggest show stoppers in IC design.
A typical comment heard during this training is,"If only we had known about (-----) before we taped that chip out..." We present real-world examples and give designers practical solutions to help them design first-time-functional chips.
Topics discussed include:
Interference Noise Problems, Noise Reduction and Floor Planning for Mixed Signal IC's
- Defining the Noise Problem
- Wideband RF coupling
- Noise Sensitivity - What's needed?
- Inherent Noise vs. Interference Noise
- Distortion vs. Interference Noise
- Top level strategy on noise
- Noise Coupling paths
- Noise as a distributed function
- Substrate Noise – A misnomer
- Power ground and substrate stability
- Splitting of power/ground domains and power isolation
- RF network problems associated with power stability
- Distributed power filtering
- Substrate Contacts
- Well Ties
- Guard Rings - The Reality
- Signal Shielding and Routing,
- Local Filtering of Analog Signals
- Floor Planning - Determining Pin Placement on an IC
- Proximity of Analog Cells and Noise Considerations
- Grouping of Logic Functions
- Separation of Digital and Analog Domains
- Reduce/Remove Noise Generation Sources
- Reduce noise sensitivity in the analog system
- Differential Circuit layout, Fully Differential Architectures
- Spectral Content: Noise vs. Desired Signal
- Processing a remote ground
- Signals off Chip, and Isolation for Control/Observation
- Signals Between Analog/Digital Parts of the IC
- Distribution of Control Bias
- Time Phase Relationships
Simulation versus Silicon
(A Designers Guide to Getting it Right the First Time!)
- Simulations - WYSIWYG or GIGO?
- Motivations & Problematic Areas
- Overlooked Concepts & Primitive Models
- Foundry Provided Models – Good, Bad & Ugly
- Is it in the model? - Limitations, Composites, Ideal vs. Reality
- Process Corners – Fact or Fiction?
- RLC & Diode Models
- Finding & Fixing Transistor Model Problems
- Impedances & Parasitics
- LPE Limitations
- ESD, I/O, Package & Bonding Issues
- Input Signals, Output Loads, Power & Ground Issues
- Simulator Limitations & Common Pitfalls
- Circuit Architecture Decisions – Yield Loss and DOA Issues
- absolute value, matched elements, top level
- feedback systems, power cycling
- noise, linearity, dynamic range, phase, timing
- Corner Testing, Layout, Access for Analysis
For more information on bringing this training seminar to your organization, contact us.
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