As part of our on-site training series, Effective Electrons offers "Practical Considerations in Mixed Signal Design." This is a nine-session training seminar with two sessions presented daily. For more information on our company and services offered, please visit the about section of our website.

Topic-by-Topic details of this program are below:

Silica to Circuit Primitives

• Moores Law
• Integrated Design vs. Discrete Design
• Physical Implementation of CMOS devices
• Silica to Silicon Wafers
• P/N materials, electrons and holes
• Lithography and physical fabrication of CMOS
• Options available on a foundry process
• CMOS vs. CPOS
• Resistor element, performance criteria, non idealities parasitics, matching, physical rendering
• Resistor layer types
• Capacitor elements, performance criteria, non idealities parasitics, matching, physical rendering
• PNP transistors in CMOS
• Inductors
• Foundry process criteria, “digital only” processes, data and model availability

CMOS Transistor Theory – the minimal equations approach

• Diodes Functionality
• Diodes On A CMOS Process
• Small Signal Model For Diode:
• FET As Realized On A CMOS Process
• Symbols For MOS Transistors
• Bulk Connections In MOS Devices
• Definition Of Device Geometry:
• Multiple Parallel Devices, M Vs. NF
• Drain/Source Differences
• Effective Length/Width and Drawn Length/Width
• Large Signal Behavior
• Threshold Voltage
• Weak, Moderate, And Strong Inversion
• Active/Saturation/Pinch-Off Region
• Bias Curve Set Regions
• Drain Current - Square Law
• Triode/Ohmic/Linear Region
• Body Effect
• Channel Length Modulation
• Effective Voltage Vs. (Vgs - Vth)
• Early Voltage
• MOS Small-Signal Modeling And Parasitics
• MOS Small Signal Model
• Gate Capacitance and Charge Injection
• Short-Channel Effects
• Enhancement/Depletion Devices
• Working With A Bias Curve Set
• Voltage Selection For Thresholds
• CMOS Versus Bipolar

Basic Building Blocks in CMOS

• Current Sources and Current Mirrors
• Source Degenerated MOS Current Mirror
• Cascode Current Source
• Wilson Current Sources
• Enhanced Output Impedance
• Wide Swing Cascode Current Mirror
• Creating A Current Reference:
• I bias Distribution
• Voltage References, and Voltage Level Shifters
• Diode Connected Devices Voltage Reference
• Threshold Voltage Multiplier
• Diodes as a Voltage Divider
• Band Gap Systems
• Band Gap Startup Circuits
• Band Gap Voltage Output over Temperature
• MOS Devices as Switches
• Charge Injection
• CMOS switch impedance as a function of voltage.
• Sample And Hold Circuits
• Parameters that define a sample and Hold Circuit

Amplifiers and Comparators

• Common Source Amplifier
• Source Follower Amplifier
• Common Gate Amplifier
• Telescopic Gain Amplifier
• Folded Cascode Amplifier
• Large Signal Considerations for all Linear Amplifiers
• Large Signal Considerations for the Source Follower:
• Functionality of the Differential Pair
• Mismatch Considerations in  Differential Pair
• Matching Differential Pairs - Common centroid layouts
• Orientation in Matching
• Proximity in Matching
• Offset and Mismatch reduction:
• Comparators - Performance Criteria
• Comparators - Basic amplifier as a Comparator
• Comparators - Push-Pull Switching
• Comparators - Push-Pull Switching and Rail to Rail Operation
• Comparators - Cross Coupled Load Device
• Comparators – Worst case response
• Comparators - Adding Hysteresis
• Comparators – Reducing Offset
• Comparators – Dynamic Compensation for Offset
• Comparators – Static Compensation for Offset

Op-Amp Design

• Ideal Op-Amp model
• Top Level Architecture
• Classic Design: 741
• Refresher - Bode Plot, Gain and Phase
• Refresher - Poles and Zeros
• Refresher - S – Plane, complex frequency plane
• Refresher - Feedback Theory
• Performance Criteria for Op-Amps
• AC Open Loop Gain/Phase
• Common-Mode Rejection Ratio
• Real world issues with CMRR
• Power-Supply Rejection Ratio
• Finite Linear Input Range
• Finite Linear Output Range
• Offset Voltage: systematic and random offset
• Slew Rate
• Non-Zero Output Resistance
• Finite DC Gain
• Properly Compensated Op-amp Characteristics
• Phase Margins vs. Response to Step Input
• Compensating an Op-Amp: Preliminary Considerations
• Different Methods of Compensation
• Output Loading
• Isolated Feedback
• Pole Splitting
• Bode Plot With/Without Compensation
• Some Common Architectures
• Operational Transconductance Amplifiers
• Methodology Outline for Op-Amp gain/compensation

Interference Noise Problems, Noise Reduction and Floor Planning for Mixed Signal IC's

• Defining the Noise Problem
• Wideband RF coupling
• Noise Sensitivity needs
• Inherent Noise vs. Interference Noise
• Distortion vs. Interference Noise
• Top level strategy on noise
• Noise Coupling paths
• Noise as a distributed function
• Substrate Noise – A misnomer
• Power ground and substrate stability
• Splitting of power/ground domains and power isolation
• RF network problems associated with power stability
• Distributed power filtering
• Substrate Contacts
• Well Ties
• Guard Rings
• Signal Shielding and Routing,
• Local Filtering of Analog Signals
• Floor Planning - Determining Pin Placement on an IC
• Proximity of Analog Cells and Noise Considerations
• Grouping of Logic Functions
• Separation of Digital and Analog Domains
• Reduce/Remove Noise Generation Sources
• Reduce noise sensitivity in the analog system
• Differential Circuit layout, Fully Differential Architectures
• Spectral Content: Noise vs. Desired Signal
• Processing a remote ground
• Signals off Chip, and Isolation for Control/Observation
• Signals Between Analog/Digital Parts of the IC
• Distribution of Control Bias
• Time Phase Relationships

Top Level Design Considerations and Chip Architecture Issues

• Bias Distribution for Large IC's
• Pin Placement &Total Number of Pins
• Latch-up
• I/O Cells – ESD and Latch-up
• Designing I/O cells
• Drain/Source/Gate/Resistor Connections Outside the Chip
• Die Size Estimates:
• Trade-offs: I/O Cells/Pin Count/Die Size/Noise/Power/Cost
• Package Selection
• Thermal Issues
• Mechanical Issues Bonding and Leadframes
• Wafer Probe Access
• Manufacturable and Testable Designs
• Limits/Restrictions of Test Systems
• ATE Considerations - Financial
• Self Testing Chips
• Test and Evaluation
• "Open " Designs vs. "Closed" Designs
• Exploded Design Methodology
• Use of probe pads
• Multifunction Pins, Hidden Modes & Control Bits
• BIST, JTAG Access
• Reducing Design Cycle Time, Critical Path Design
• Not Invented Here, Design Re-use
• Tape out, debug, getting to Manufacture 
• Wafers “on hold,” Contingency Circuit Elements, Multi Mask Strategies
• After Fabrication Modifications
• Automated Test Systems (ATE)
• IC Economics: Costs and Yields
• Defect Density Yield Loss, Overall Product Yield
• IC Additive Cost Analysis
• Picking a Foundry Process, Getting Fabricated At Low Cost

ADC’s and DAC’s

• Interface to the analog world
• Common Concepts
  • Refresher: Nyquist Rate
  • Refresher: Aliasing
  • Refresher: Pipelined Processes
• Overview of Conversion Process
• Typical Analog Input Signal
• Items Common to ADC systems
• Items Common to DAC systems
• Nyquist Rate vs. Over sampling Converters
• Interface Code Structures
• DAC's, Performance Criteria
  • Linear Output Range
  • Resolution
  • Conversion Rate
  • Differential non linearity (DNL)
  • Integral non linearity (INL)
  • Offset
  • Gain error
  • Monotonic Transfer Function
  • Settling TIme
  • Glitch Impulse Energy
  • Latency
  • SNDR
  • SFDR
• Common DAC Structures
  • Resistor String
  • Sub Ranging Resistor String
  • R-2R Ladder
  • Current Steering
  • Thermometer Code Control
  • Segmented Architecture
  • Over sampling PCM, PWM, Sigma-Delta
• ADC's, Performance Criteria
  • DNL
  • INL
  • Offset
  • Gain error
  • Linear Input Range:
  • Conversion Rate
  • Resolution
  • ENOB
  • Dynamic performance of converters
• Conversion Residues
• Common ADC Structures
  • Flash Converters
  • Bubble/Sparkle Problems WIth Flash Converters
  • Two Step Converters
  • Successive Approximation Converter
  • Dual Slope Converter
  • Pipeline Converter
• Interleaved Converters

Simulation versus Silicon
(A Designers Guide to Getting it Right the First Time!)

• Simulations - WYSIWYG or GIGO?
• Motivations & Problematic Areas
• Overlooked Concepts & Primitive Models
• Foundry Provided Models – Good, Bad & Ugly
• Is it in the model? - Limitations, Composites, Ideal vs. Reality
• Process Corners – Fact or Fiction?
• RLC & Diode Models
• Finding & Fixing Transistor Model Problems
• Impedances & Parasitics
• LPE Limitations
• ESD, I/O, Package & Bonding Issues
• Input Signals, Output Loads, Power & Ground Issues
• Simulator Limitations & Common Pitfalls
• Circuit Architecture Decisions – Yield Loss and DOA Issues
  • absolute value, matched elements, top level
  • feedback systems, power cycling
  • noise, linearity, dynamic range, phase, timing
• Corner Testing, Layout, Access for Analysis